The present invention relates to a microprocessor designed especially but not solely to be integrated into a chip card, and more particularly into a contactless inductive type chip card.
Inductive contactless chip cards, supplied by electromagnetic induction, have to comply with contradictory technical constraints. First of all, their electrical- power resources are low and depend on the distance between the antenna coil and the supply coil of a card reader. This distance, which about a few centimeters, may vary greatly depending on the user""s movements in such a way that the supply voltage received by induction may fluctuate greatly and become very low. Furthermore, contactless chip cards provide high operating speed ensuring fast processing of electronic transactions. For example, a chip card of the electronic badge type used for access control is presented to the user before a control terminal. The period of time during which the card is presented before the terminal must be short, about a few milliseconds. During this period, the card is electrically powered by induction and must carry out several operations such as the production and sending of an authentication code, the sending of an authentication number, possibly the recording in its memory of the xe2x80x9cdoor opening requestxe2x80x9d event, date, place, etc.
Now, the increase in operating speed of an integrated circuit, especially a CMOS technology circuit, is associated with an increase in electrical power consumption. A contactless chip card microprocessor must therefore be fast while at the same time consuming little current.
It has been the practice hitherto, in chip cards with contacts, to use microprocessors of simple but old design. Their only advantage ultimately was that they cost little and were compact in terms of silicon surface area. With the appearance of contactless chip cards, these microprocessors are seen to be obsolete and incapable of meeting the above-mentioned constraints.
There also exist known sophisticated pipeline type microprocessors, namely microprocessors with overlapping of instructions. The advantage of these microprocessors is that they work at high speed. However, these microprocessors have a degree of complexity, space requirement and cost price that makes them unsuitable for integration into chip cards.
The goal the present invention is to provide for a microprocessor that, at the same time, is simple in design and compact and consumes little power, while providing high-speed processing of the instructions of a program.
To achieve this goal, the idea of the present invention is to make a pipeline type microprocessor in order to benefit from the advantages of the overlapping of instructions wherein the processing of the instructions of the program is done in a minimum number of pipeline cycles with the intervention of a minimum number of a pipeline stages in a simpler way so as to reduce the number of logic gates simultaneously activated and the electrical power consumption.
More particularly, the present invention provides for a pipeline microprocessor comprising a first pipeline stage comprising means for reading and decoding instructions of a program recorded in a memory, a second pipeline stage contiguous to the first pipeline stage, comprising two sectors activated one after the other during complementary half-cycles of a clock signal of the microprocessor, the first sector comprising means to read pieces of data contained in two registers of a bank of registers of the microprocessor and carry out an operation on the data according to an instruction received at the previous clock cycle by the first pipeline stage, the second sector comprising means to record the result of the operation in a register of the bank of registers.
According to one embodiment, the first pipeline stage comprises two sectors activated during the complementary half-cycles of the clock signal, the first sector of the first pipeline stage comprising means for reading the instructions in the memory, the second sector of the first pipeline stage comprising means for decoding the instructions.
According to one embodiment, the first sector of the second pipeline stage comprises an arithmetic and logic unit and a shift circuit.
According to one embodiment, the first sector of the second pipeline stage comprises means to carry out the concatenation of a bit of a first binary word with bits of a second binary word in one clock half-cycle.
According to one embodiment, the reading and decoding means are arranged to decode compact instructions comprising an instruction code, an address of a first register and an address of a second register of the bank of registers.
The present invention also relates to a pipeline microprocessor comprising means for reading and means for decoding instructions of a program recorded in a memory, a bank of registers and data computation and processing means in which the read means and the decoding means are laid out in a first pipeline stage, the computation and processing means are laid out in a first sector of a second pipeline stage contiguous to the first pipeline stage, the first sector being activated during a first half-cycle of a clock signal of the microprocessor, the bank of registers is laid out in read mode in the first sector of the second pipeline stage and in write mode in a second sector of the second pipeline stage, the second sector being activated during a second clock half-cycle.
According to one embodiment, the memory is laid out in write mode in the second sector of the second pipeline stage.
According to one embodiment, the computation and processing means comprise means for the performance, in one clock half-cycle, of an operation to concatenate a bit of a first binary word with bits of a second binary word.
The present invention also relates to a method for the processing of an instruction read in a memory by a microprocessor comprising a bank of registers, means for decoding the instruction and means for executing the instruction, comprising a first step for extracting a first address, a second address and an operation code contained in the instruction, with a maximum duration of one clock cycle of the microprocessor, a second step for the simultaneous reading of a first register and a second register of the bank of registers identified by the addresses extracted from the instruction during the first step and for carrying out, on the basis of the contents of the registers, an arithmetic or logic operation identified by the operation code of the instruction, with a duration of one clock half-cycle, and a third step for the recording of the result of the operation in a register of the bank of registers, with a duration of one clock half-cycle.
According to one embodiment, the result is recorded in one of the first and second registers.